One or more embodiments relate to a nonvolatile memory device and a method of operating the same.
Recently, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and do not require the refresh function of rewriting data at specific intervals.
A nonvolatile memory cell enables an electrical program/erase operation and performs the program and erase operations through threshold voltages varying when electrons are migrated by a strong electric field applied to a thin oxide layer.
When the program operation of this nonvolatile memory device is performed, the threshold voltages of cells do not have the same value, but are distributed with some degree of variation. With wide distributions of the threshold voltages, read margin is narrowed, thereby deteriorating the property of the nonvolatile memory device. In particular, in the case where there exist three or more different distributions as in a Multi-Level Cell (MLC) program method, it is more preferred that the distribution in each state is limited to a narrow range. However, as the size of each cell shrinks with the high integration of a memory device, abnormal phenomena is generated, so the distribution becomes wider.
All the distributions of threshold voltages of a nonvolatile memory device using a known Incremental Step Pulse Program (ISPP) method are determined by various factors, such as an under program phenomenon, the step voltage of ISPP, floating gate interference, bit line coupling noise, and abnormal phenomena.
In particular, one or more embodiments are directed to solving an under program phenomenon generated by the source line bouncing phenomenon, the increase in the distributions of threshold voltages resulting from bit line coupling noise, and so on.